1. Field of the Invention
The present invention relates in general to electronic memories and in particular to glitch-free memory address decoding circuits and methods and memory subsystems using the same.
2. Background of Invention
A typical electronic memory system, such as a random access memory (RAM) system or a read-only memory (ROM) system, is based on an array of rows and columns of memory cells. Depending on the architecture, these memory cells are organized into data storage locations for storing data words of a given width. For example, in a “16 by 16” memory system, data are stored as 16-bit wide words in 16-column wide locations along a corresponding row. Data are then accessed (read and written) to a given location at the intersection of the corresponding row and columns using associated row and column addresses.
In synchronous memory systems, row and column addresses are latched into an address register and held until the next set of row and column addresses arrives. The current address in the address register is decoded into row and column select signals which control the selection of the rows and columns corresponding to the addressed location. Once these row and column signals have settled into the proper state, the decoder outputs are enabled, and the access is performed.
The process of latching and decoding each address, including allowing the decoder outputs to settle, requires a finite, although variable, time period. If the decoder outputs are enabled before this process is complete, glitches may occur which corrupt the data and/or misdirect the access to the wrong memory location. These glitches may also add noise to the system and cause excess power dissipation. Hence, a time delay is typically introduced between address latching and decoder output enablement to allow for circuit activation and signal settling. This delay normally includes sufficient margin to account for fabrication process, voltage and temperature variation, noise, and similar factors that impact circuit timing.
Designing timing circuitry to provide the sufficient timing margins required to ensure glitch-free memory operation across a range of fabrication and operating variables is a relatively complicated effort. For example, the timing margins should be minimized since holding-off the enablement of the decoder outputs directly increases the time to access the array. In high-speed memory systems, minimized access time is a critical design parameter. On the other hand, decoder output enablement must be delayed by a sufficient amount of time to avoid the problem of glitches described above. Hence, new circuits and methods are required which relax the design constraints on the access timing circuitry while still allowing high-speed glitch-free accesses.